The present invention relates to an electronic circuit for accumulating signals representing the translation of vehicle or the like, including provisions for storing the signal counts in nonvolatile memory during periods when the vehicle power is disabled. More particularly, the invention provides a structured arrangement for initializing, accumulating and storing in nonvolatile form digital representations of translation information using conventional EEPROM architecture with memory mapped shifting of addresses to allocate endurance degradation effects in relative relation to the significance of the data being stored.
The endurance limitations of nonvolatile memory arrays are well known to designers of electronic circuits. Whether the degradation is characterized by a reduction of the data window or an extension of the erase/write time periods, designers of circuits including nonvolatile devices routinely configure the circuits to specifically control the number of erase/write cycles experienced by each identified nonvolatile device. On the other hand, nonvolatile devices are conventionally designed to allow a substantially unlimited number of read cycles without affecting the data content being addressed.
Designers of digital electronic devices for automotive applications clearly recognize that vehicle translation measurement devices, odometers, must be capable of storing the data in nonvolatile form, in the event the vehicle power is briefly interrupted, e.g. during a battery change, or extendedly absent. Furthermore, odometer accuracy requirements mandate that the stored information must be updated with sufficient frequency to correctly represent the actual distance travel by the vehicle.
The fundamental problems have been the subject of investigation by various circuit designers. Unfortunately, the solutions tend to be extremely complex, both in the architecture of the circuit implementation, which defines the functional blocks and their interconnection, as well as the elaborate and interrelated operations performed by the functional blocks. Furthermore, the known designs are highly particularized to a prescribed arrangement of odometer characters, thereby requiring major revisions of the architecture for superficially minor changes in the number of odometer digits or endurance characteristics of the nonvolatile device.
For example, U.S. Pat. No. 4,528,683 implements an odometer using a highly particularized five-bit word per decimal position counting scheme with a multi-level multiplexer to provide an elaborate permutation of nonvolatile memory addresses for distributing endurance degradation among cells. Movement of the decimal ones, tens, hundreds and thousands, position through the memory array is used to spread the erase cycle "wear" effects throughout the memory array. Thereby, the numerous erase/write cycles associated with the decimal ones digit are shared by the memory array cells. Typical nonvolatile memories cells begin to exhibit endurance degradation after approximately 10,000 erase/write cycles.
The approach taken in U.S. Pat. No. 4,663,770 is somewhat different, in that the counters themselves are the nonvolatile storage devices. Counter usage from the least to the most significant bit positions is successively shifted to distribute the erase/write cycle degradation effects among the various counter stages. Though the architecture distributes the erase/write "wear" among nonvolatile devices within the system, the coding and decoding of such distributed use is complex both in conceptual implementation and hardware configuration. Refinements are obviously difficult to implement.
Accordingly, there exist a need for a design of conventional architecture which is readily amenable to refinements and improvements at incremental levels, can be implemented with relatively conventional electronic devices, and allocates endurance degradation in relative relation to the significance of the decimal count position.